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eDigiM Research Private Limited
About eDigiM
At eDigiM, we are a dynamic startup at the forefront of the Semiconductor and Embedded systems industries, delivering innovative solutions to clients around the world. Our unwavering focus on quality and customer satisfaction has fueled our rapid growth, making us one of the fastest-growing companies in our field.
Started four years ago, we've reached significant milestones, expanding our reach to over few global customers across diverse regions, including India, Taiwan, USA, Canada, and Malaysia. Our relentless commitment to excellence has been the cornerstone of our success, and we take immense pride in the remarkable journey we've undertaken.
Expertise and Strength:
At eDigiM, our engineering team consists of over 50+ highly skilled and dedicated professionals, bringing deep expertise across a wide range of domains. Our capabilities include ASIC/RTL Design, IP/SoC Verification, Physical Design & STA, FPGA Design, Design for Testability. Also we are working on product development in Embedded and IoT.
Business Models:
We have the right set of teams, experts who can manage & execute Turnkey, Fixed Quote, ODC & Resource Augmentation requirements.
We are open to operate in any of the below mentioned business models. We are also open for any new suggestion in business model.
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Staff/Resource Augmentation – Time & Material / Full-Ownership
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Offshore Development Center – Full Ownership / Time & Material / Turnkey mode
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Turnkey Projects – for IP development / SoC development / Board Design
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Build Operate and Transfer (BOT) Model
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Co-Development and Co-Ownership of IPs
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Responsible for configurable IP verification process flow development and track to ensure on time delivery and bug free design through reusable test bench, firmware verification early in the design, process automation and formal verification.
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Experience in developing testbench, bfmand uvc’s using system Verilog and UVM methodologies for data path and control path related designs.
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Experience in creating test plan, functional coverage plan for block level and soc level verification and closure though coding testcases, writing checkers, functional coverage and code coverage measurement.
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Experience on simulation and debugging tools like Cadence Ncsim, IFV, simvision and Synopsys VCS, Verdi.
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Experience on formal verification using SVA, PSL with VC Formal and Cadence IFV.
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Experience in DPI based firmware API and ARM M0 based boot code functional verification.
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Worked on Ethernet MAC standard IEEE 802.3, L2/L3 layers and serdes based design core verifications.
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Experience in SOC protocols like AXI, APB, CAN and JDEC DDR3/DDR4 Memory interface standards.
Expertise in place & route for block build/full chip development with timing closure using industry standard tools for tasks like Synthesis, Floor Plan, Placement, CTS, Signal Integrity, IR Draw, EM, Low Power Checks and Signoff checks. Extensive Knowledge in physical verification like DRC, LVS, Antenna, Density in latest nodes like 14nm, 10nm. Experience in DFT Techniques like Scan, Bist, ATPG, Boundary Scan.
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We are providing End to End Solutions for Deign For Testability .
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Drive end-to-end DFT (Design for Test) solutions in chip design by collaborating closely with the chip DFT team to:
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Define and document DFT specifications and SoC test interfaces.
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Develop and implement robust DFT architectures.
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Partner with the validation team to verify DFT implementations and incorporate necessary design changes.
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Generate structural test vectors, analyze test coverage, and optimize for improved coverage.
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Collaborate with design teams to address STA, physical, power, and logic-related issues.
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Work with Test Engineers to bring up and debug test vectors on silicon.
Expertise in Layout of analog components like ADC, DAC, PLL, Bandgap, Power regulators etc. Experience in designing standard cell libraries that meet several design criteria like optimal area, power, timing etc. on several technology nodes. Specialists in high speed high density memories and associated modules. In depth understanding of design of IO cells and interfaces having unique electrical and noise specifications.
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